6510 compatibility only requires adding 6 IO lines mapped to address $1 though (otherwise the 6510 is 6502 compatible enough), so given it's an FPGA based project it wouldn't necessarily be a big ask, and from the webpage it sounds like they're open to suggestions.
I don't think memory at $00 and $01 are the only challenges. The 6510 has a tristateable bus. A regular 6502 doesn't. The C64 used this to disable the 6510 when the Z80 in the cp/m card was active. (I think it also might be used to allow the VIC II to take over the bus as well, but I'm not positive about that.)
Actually the bigger problem with this design on a second read through is that it tries to mirror the ROM and RAM into a 64K on-chip RAM. That won't work on the C64 because of the bank switching and the fact the VICII can access memory everywhere. You'd have to change it to use the on-chip RAM as a smarter cache.
If you were to disable the use of the on-chip RAM it'd be stalled far more than half the time, as it'd be unable to fetch instructions fast enough.
The bank switching uses three of the IO pins, so if you add support for those as I mentioned that fixes both the bank switching and the tape drive (which uses the remaining IO pins).
EDIT: Actually you're right that there's a problem with the bank switching here since it tries to mirror the system RAM/ROM, and it won't be able to as it has only 64K on-chip RAM. You could conceivable get it to work by designating the entire address space as an "IO area" but it'd totally kill performance.
