> or introduce a separate parallel chip alongside the binned ones that actually targets their specs (which you would still have to bin downward).
you know, I hadn't actually thought of that. If you did this, presumably it would involve the cost of setting up another manufacturing line, (colossal), and you'd _still_ have binning issues. Presumably the tolerances would be looser however; if you can build within 5% power usage of X, you should be able to _easily_ build within 5% power usage of (x/2).
you know, I hadn't actually thought of that. If you did this, presumably it would involve the cost of setting up another manufacturing line, (colossal), and you'd _still_ have binning issues. Presumably the tolerances would be looser however; if you can build within 5% power usage of X, you should be able to _easily_ build within 5% power usage of (x/2).
Interesting thoughts.