When multiple cores access the same memory location, it is expensive for one core to invalidate the cache of another or ensure operations don't get re-ordered in either core. These days most architectures when reading or writing shared data require memory barrier instructions to guarantee your core to sees writes from another, or other cores to see your writes, in a timely sequential fashion like we expect when writing code that accesses variables.
Historically there were architectures that would reorder these accesses in a "lax" way, making very few guarantees about what you will see from another core, on the theory that it will cost less to keep things synchronized between cores (most data is not shared anyway, so why waste work trying to create a unified view across cores? The CPU can also reorder work for better efficiency.). Intel is historically one of the most conservative, strict-ordering architectures, requiring fewer barrier instructions and creating the illusion that reads and writes more or less occur on a single timeline.
