> Idle states are not free to enter or exit. Entry and exit both require some time, and moreover power consumption briefly rises slightly above normal for the current state on entry to idle and above normal for the destination state on exit from idle. Although increasingly deep idle states consume decreasing amounts of power, they have increasingly large costs to enter and exit.
What causes this? I would have thought that "stop computing for a bit" would be a simple thing to do, but I clearly don't know much about processor design.
I work in CPU design. It all comes down to saving power given how frequent idle-state entries are (especially C1 enters with almost most wait-for-interrupt operations) Stop-computing isn't well defined. As long as the clock ticks, the frontend will keep fetching instructions. Sure you can keep feeding it NOPs, but instead, we save power by entering idle states.
The quickest to enter and exit (C1) simply clock-gates the core. Caches are preserved. The next c-state might turn off caches too (and thus incurs the penalty of flushing caches on entry and starting with a cold cache on c-state exit). Further C-states might require even more work to enter and exit but consume much lesser power when in that state.
The cpuidle governor decides which C-state to enter since a deep C-state entry and exit may end up consuming even more power than keeping the system running or in C1.
Usually there is a change in voltage on the processor when the processor changes state. This change in voltage expends energy due to the capacitance of the power rail and the circuit itself (the capacitance of one transitor itself is small but there are billions of them).
Even if there is no change in voltage usually the processor will just leak power while making no forward progress on the program while the various timing circuits change.
What causes this? I would have thought that "stop computing for a bit" would be a simple thing to do, but I clearly don't know much about processor design.