That is correct. We have FPGAs, qemu, and formal models (that can boot an OS) of CHERI-RISC-V and CHERI-MIPS. Most software development uses qemu as it is faster than the FPGAs at around 100MHz.
Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.
We (University of Cambridge) have added it to MIPS and RISC-V. As the same team did both of these they feel similar. Arm is working closely with us to add it to their architecture, but it has a few differences, mostly to allow for experimentation to see what should be added to the future production architecture.
There will be a simulator later this year. I expect CheriBSD on Morello will released at the same time with a feature set compariable with MIPS and RISC-V.
There is a RISC-V section as we (I work on CHERI) are interested in making sure it's a portable model. There's no point creating this if we can only ever use it on MIPS.
booting on the Dragonboard is unlikely to happen any time soon, I started working on it, but don't have the time to get it into a usable state (and lack hardware to test).
Source: I started & mostly work on the the FreeBSD arm64 port.
RISC-V seems to be lacking on the software side, e.g. where is the upstream support for Linux, GCC, or llvm? There is support in FreeBSD, but only because one of the FreeBSD committers was able to work on this full time (I've been providing advice to him as I ported FreeBSD to arm64 & have an office next to his).
I also have issues with the fact that many parts of the ISA are optional. A general purpose OS needs some common level of support by the hardware. If it can't rely on some features it makes it difficult to support the different SoCs.
IIRC there are ISA changes that need to be finalised before the support goes upstream. The support is already developed and available on github though.
Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.