You mean the kind of "first" that comes right after shattered screens, worn batteries, and loose charging ports? :P
I agree in spirit though: storage chips wearing out seems to be common from my limited experience and it would be good if you could solder on, or slide in, a new chip with some standard procedure
Sure, but you said storage chips wearing out is the first thing that fails in a device
And battery replacements usually leave devices in a degraded state, not sure about screen or charging port, so it's still good that this becomes more accessible
It might be a bit CPU and RAM starved… Which in theory should be OK, but in practice you'll find production workloads that struggle because of this. Just make sure whatever you want to run on this is indeed extremely GPU-bound, or you might have bad surprises later.
Thanks for the context. Since I'm not interested in betting, I had not clicked on the grey on white About link at the bottom, which says:
> All the trains, delays, and data on this app are real.But the money isn't – because for that I'd need to move to Malta. Or Cyprus. Or Schleswig-Holstein.
It would be fun if Google lost its months of edge in the LLM value race because it alienated early adopters paying $250/month by using a 0-strike system with no customer support.
Honestly, I think it was probably a few users abusing the system like crazy. I've been building with Gemini CLI the past few days and had an increasing amount of issues getting a request through.
The GH issue trackers were full of people bitching and moaning about it. I think it might be a worse thing to alienate your users who use your product in the intended way - through Google's tooling.
But I agree the 0 strike rule seems really excessive.
It is also a possible scenario that a single individual sets up 10+ AI Pro subscriptions to blast through tokens like crazy - not sure how the economics of the daily allowances compare to the API pricing here.
That's a lot of surface, isn't it? As big an M1 Ultra (2x M1 Max at 432mm² on TSMC N5P), a bit bigger than an A100 (820mm² on TSMC N7) or H100 (814mm² on TSMC N5).
> The larger the die size, the lower the yield.
I wonder if that applies? What's the big deal if a few parameter have a few bit flips?
Also see Adrian Thompson's Xilinx 6200 FPGA, programmed by a genetic algorithm that worked but exploited nuances unique to that specific physical chip, meaning the software couldn't be copied to another chip. https://news.ycombinator.com/item?id=43152877